CD budget analysis on sub-50-nm DRAM device: global CD variation to local CD variation

Chan Hwang; Joon-Soo Park; Jeongho Yeo; Seong-Woon Choi; Chan-Hoon Park

doi:10.1117/12.814476

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23 March 2009 CD budget analysis on sub-50-nm DRAM device: global CD variation to local CD variation

Chan Hwang, Joon-Soo Park, Jeongho Yeo, Seong-Woon Choi, Chan-Hoon Park

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Proceedings Volume 7272, Metrology, Inspection, and Process Control for Microlithography XXIII; 72722O (2009) https://doi.org/10.1117/12.814476
Event: SPIE Advanced Lithography, 2009, San Jose, California, United States

Abstract

In this study, overall critical dimension (CD) error budget analysis procedure is proposed to estimate the source of CD error. Until now, local CD variation has been treated as noise or uncertainty, since it has been considered not real, and it is difficult to be measured. However, the actual measurement result shows the local CD variation occupies a significant portion of overall CD variation. We included the local variation into overall CD budget analysis, and performed the budget break-down of the local CD variation. This analysis was performed on the layers of a sub-50nm DRAM device. We calculated local CD uniformity from CD SEM measurement data having multi-point measurement on each frame. Metrology error of wafer CD SEM and mask CD SEM was measured, and local CD uniformity (CDU) of mask was also measured. To estimate the impact from the mask local CDU, we performed simulation with a virtual mask shape which has the same level of local variation with real mask. The remaining budget, except metrology and mask induced budget, is treated as a process roughness. To predict the budget caused by process roughness, a randomly varying threshold map was applied. In this approach, the local CD variation of 2-dimensional patterns is considered as an extension of the LWR in 1-dimension.

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Chan Hwang, Joon-Soo Park, Jeongho Yeo, Seong-Woon Choi, and Chan-Hoon Park "CD budget analysis on sub-50-nm DRAM device: global CD variation to local CD variation", Proc. SPIE 7272, Metrology, Inspection, and Process Control for Microlithography XXIII, 72722O (23 March 2009); https://doi.org/10.1117/12.814476

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