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23 March 2009Optimization of alignment strategy for metal layer on local interconnect integration
The influence of processing on wafer alignment is becoming an increasingly important issue. We need to improve an
overlay accuracy and alignment performance when design rule are reduce. Especially, the alignment of Metal layers
gets some process effects, then we should have prepared to prevent alignment error by the wafer loss and reducing
throughput.
Alignment of Metal 0 layer in the local interconnect integration is much affected by ILD thickness, resist coating
process, but also there are effective phase depth.
In this paper, new alignment strategy is presented by simulation of stack structure impact on alignment. We are able
to accomplish the increase of alignment signal intensity by new alignment strategy. In addition, we can be achieved
alignment robustness to process variation for M0 to M0C alignment of local interconnect.
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Jun-Kyu Ahn, Ji-Hyun Ha, Hong-Ik Kim, Jeong-Lyeol Park, Jae-Sung Choi, Tae-Jong Lee, "Optimization of alignment strategy for metal layer on local interconnect integration," Proc. SPIE 7272, Metrology, Inspection, and Process Control for Microlithography XXIII, 727233 (23 March 2009); https://doi.org/10.1117/12.814434