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1 April 2009 Fabrication of 22-nm poly-silicon gate using resist shrink technology
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Abstract
Exposure wave length has been changing rapidly with the shrink of design rule. In 32nm node and beyond, it is predicted that keeping good resolution performance of resist pattern with small dimension and high density will be more difficult due to the drop of optical contrast in 193nm immersion lithography. EUV lithography and Double Patterning using 193nm immersion lithography are being investigated as alternative technologies, but it is currently difficult to keep enough process margins in device fabrication. Resist slimming technology by dry process and exposure process is also being investigated based on these technical backgrounds but many technical challenges have been reported. We started to develop our original resist slimming technology in track process with the aim of overcoming technical challenges and cost reduction, which is one of main challenges in double pattering. In this paper, we report the basic characteristics of our resist slimming process (controllability of CD shrink, CD uniformity within wafer, LWR, and total process margin) and also pattern transfer performance of CD and LWR after dry etching in order to apply this slimming technology to Double Pattering.
© (2009) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Fumiko Iwao, Satoru Shimura, Tetsu Kawasaki, Masato Kushibiki, and Nishimura Eiichi "Fabrication of 22-nm poly-silicon gate using resist shrink technology", Proc. SPIE 7273, Advances in Resist Materials and Processing Technology XXVI, 72730G (1 April 2009); https://doi.org/10.1117/12.814365
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