Paper
1 April 2009 Backside EBR process performance with various wafer properties
Author Affiliations +
Abstract
In immersion lithography process, film stacking architecture will be necessary to avoid top coat film peeling. To achieve suitable stacking architecture for immersion lithography process, an EBR process that delivers tightly controlled film edge position and good uniformity around the wafer circumference is needed. We demonstrated a new bevel rinse system on a SOKUDO RF3 coat-and-develop track for immersion lithography. The performance of the new bevel rinse system for various wafer properties was evaluated. It was found that the bevel rinse system has a good controllability of film edge position and good uniformity around the wafer circumference. The results indicate that the bevel rinse system has a large margin for wafer centering accuracy, back side particles, wafer shape and substrates with good film edge position controllability, uniformity and clean apex. The system has been demonstrated to provide a suitable film stacking architecture for immersion lithography mass production process.
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Tomohiro Goto, Kazuhito Shigemori, Rik Vangheluwe, Daub Erich, and Masakazu Sanada "Backside EBR process performance with various wafer properties", Proc. SPIE 7273, Advances in Resist Materials and Processing Technology XXVI, 727329 (1 April 2009); https://doi.org/10.1117/12.814079
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KEYWORDS
Semiconducting wafers

Immersion lithography

Particles

Thin film coatings

System integration

Coating

Chemical vapor deposition

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