Resist process control for 32-nm logic node and beyond with NA > 1.30 immersion exposure tool

Seiji Nagahara; Kazuhiro Takahata; Seiji Nakagawa; Takashi Murakami; Kazuhiro Takeda; Shinpei Nakamura; Makoto Ueki; Masaki Satake; Tatsuhiko Ema; Hiroharu Fujise; Hiroki Yonemitsu; Yuriko Seino; Shinichiro Nakagawa; Masafumi Asano; Yosuke Kitamura; Takayuki Uchiyama; Shoji Mimotogi; Makoto Tominaga

doi:10.1117/12.813498

1 April 2009 Resist process control for 32-nm logic node and beyond with NA > 1.30 immersion exposure tool

Seiji Nagahara, Kazuhiro Takahata, Seiji Nakagawa, Takashi Murakami, Kazuhiro Takeda, Shinpei Nakamura, Makoto Ueki, Masaki Satake, Tatsuhiko Ema, Hiroharu Fujise, Hiroki Yonemitsu, Yuriko Seino, Shinichiro Nakagawa, Masafumi Asano, Yosuke Kitamura, Takayuki Uchiyama, Shoji Mimotogi, Makoto Tominaga

Author Affiliations +

Proceedings Volume 7273, Advances in Resist Materials and Processing Technology XXVI; 72733A (2009) https://doi.org/10.1117/12.813498
Event: SPIE Advanced Lithography, 2009, San Jose, California, United States

Abstract

Resist process challenges for 32-nm node and beyond are discussed in this paper. For line and space (L/S) logic patterns, we examine ways to balance the requirements of resolution-enhancement techniques (RETs). In 32-nm node logic patterning, two-dimensional (2D) layout pattern deformation becomes more severe with stronger RET (e.g., narrow angle CQUAD illumination). Also pattern collapse more frequently happens in 2D-pattern layouts when stronger RET is used. In contrast, milder RET (annular illumination) does not induce the severe pattern collapse in 2D-pattern layout. For 2D-pattern layouts, stronger RET seems to worsen image contrast and results in high background-light in the resist pattern, which induces more pattern collapse. For the minimum-pitch L/S pattern in 32-nm node logic, annular illumination is acceptable for patterning with NA1.35 scanner when high contrast resist is used. For contact/via patterns, it is necessary to expand the overlapping CD process window. Better process margin is realized through the combination of hole-shrink technique and precise acid-diffusion control in an ArF chemically amplified resist.

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Seiji Nagahara, Kazuhiro Takahata, Seiji Nakagawa, Takashi Murakami, Kazuhiro Takeda, Shinpei Nakamura, Makoto Ueki, Masaki Satake, Tatsuhiko Ema, Hiroharu Fujise, Hiroki Yonemitsu, Yuriko Seino, Shinichiro Nakagawa, Masafumi Asano, Yosuke Kitamura, Takayuki Uchiyama, Shoji Mimotogi, and Makoto Tominaga "Resist process control for 32-nm logic node and beyond with NA > 1.30 immersion exposure tool", Proc. SPIE 7273, Advances in Resist Materials and Processing Technology XXVI, 72733A (1 April 2009); https://doi.org/10.1117/12.813498

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KEYWORDS

Resolution enhancement technologies

Logic

Optical lithography

Line width roughness

Photoresist processing

Lithography

Copper

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