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16 March 2009 Demonstration of 32nm half-pitch electrical testable NAND FLASH patterns using self-aligned double patterning
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Abstract
Self-Aligned Double patterning (SADP) technology has been identified as the main stream patterning technique for NAND FLASH manufacturers for 3xnm and beyond. This paper demonstrates the successful fabrication of 32nm halfpitch electrical testable NAND FLASH wordline structures using a 3-mask flow. This 3-mask flow includes one critical lithography step and two non-critical lithography steps. It uses a positive tone (spacer as mask) approach to create 32nm doped poly wordlines. Electrical measurements of line resistance are performed on these doped poly wordlines to demonstrate the capability of this patterning technique. Detailed results and critical process considerations, including lithography, deposition and etch, will be discussed in this paper.
© (2009) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Shiyu Sun, Chris Bencher, Yongmei Chen, Huixiong Dai, Man-Ping Cai, Jaklyn Jin, Pokhui Blanco, Liyan Miao, Ping Xu, Xumou Xu, James Yu, Raymond Hung, Shiany Oemardani, Osbert Chan, Chorng-Ping Chang, and Chris Ngai "Demonstration of 32nm half-pitch electrical testable NAND FLASH patterns using self-aligned double patterning", Proc. SPIE 7274, Optical Microlithography XXII, 72740D (16 March 2009); https://doi.org/10.1117/12.814403
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