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16 March 2009 Alignment and overlay improvements for 3x nm and beyond process with CVD sidewall spacer double patterning
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Sidewall Spacer Double Patterning (SSDP) has been adopted for the primary patterning technique for 3x nm technology node and beyond in flash memory device manufacturing. Three mask flow are used in SSDP process scheme in order to form the actual device layer; Core mask to define the template pattern, Trim mask to cut (cropping) the unneeded line ends from sidewall spacer, and Pad mask to pattern the periphery structures. Inter-layer and intra-layers alignment with sidewall spacer double patterning requires some engineering efforts compared to traditional single patterning alignment techniques. In this paper, we study the impacts of hard-mask materials on the inter-layer alignment as well as the mark design and process flow impact on intra-layer alignment. For intra-layer alignment, we searched various ASML ATHENA alignment marks and found the only workable mark (VSPM-AA157 Polar). Although the wafer quality scores during alignment were less than 0.1% in many cases, the alignment was successful and yielded acceptable performance for research and development activities requiring less than 10nm misalignment. Further new mark design and test should be carried in implementing in sidewall spacer double patterning process.
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Huixiong Dai, Chris Bencher, Yongmei Chen, Shiyu Sun, Xumou Xu, and Chris Ngai "Alignment and overlay improvements for 3x nm and beyond process with CVD sidewall spacer double patterning", Proc. SPIE 7274, Optical Microlithography XXII, 72743G (16 March 2009);

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