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As design rules and corresponding logic standard cell layouts continue to shrink node-on-node in
accordance with Moore's law, complex 2D interactions, both intra-cell and between cells, become much
more prominent. For example, in lithography, lack of scaling of λ/NA implies aggressive use of resolution
enhancement techniques to meet logic scaling requirements-resulting in adverse effects such as
'forbidden pitches'-and also implies an increasing range of optical influence relative to cell size. These
adverse effects are therefore expected to extend well beyond the cell boundary, leading to lithographic
marginalities that occur only when a given cell is placed "in context" with other neighboring cells in a
variable design environment [1]. This context dependence is greatly exacerbated by increased use of strain
engineering techniques such as SiGe and dual-stress liners (DSL) to enhance transistor performance, both
of which also have interaction lengths on the order of microns. The use of these techniques also breaks the
formerly straightforward connection between lithographic 'shapes' and end-of-line electrical performance,
thus making the formulation of design rules that are robust to process variations and complex 2D
interactions more difficult.
To address these issues, we have developed a first-principles-based simulation flow to study contextdependent
electrical effects in layout, arising not only from lithography, but also from stress and
interconnect parasitic effects. This flow is novel in that it can be applied to relatively large layout clips-
required for context-dependent analysis-without relying on semi-empirical or 'black-box' models for the
fundamental electrical effects. The first-principles-based approach is ideal for understanding contextdependent
effects early in the design phase, so that they can be mitigated through restrictive design rules.
The lithographic simulations have been discussed elsewhere [1] and will not be presented in detail. The
stress calculations are based on a finite-element method, extrapolated to mobility using internal algorithms.
While these types of calculations are common in '1D' TCAD space, we have modified them to handle ~10
μm X 10 μm clips in reasonable runtime based on advances in software and optimization of computing
resources, structural representations and simulation grids.
In this paper, we discuss development and validation of the simulation flow, and show representative
results of applying this flow to analyze context-dependent problems in a 32-nm low-power CMOS process.
Validation of the flow was accomplished using a well-characterized 40/45-nm CMOS process
incorporating both DSL and SiGe. We demonstrate the utility of this approach not only to establishing
restrictive design rules for avoiding catastrophic context-dependent effects, but also to flag individual cells
and identify cell design practices that exhibit unacceptable levels of context-dependent variability. We
further show how understanding the sources of stress variation is vital to appropriately anchoring SPICE
models to capture the impact of context-dependent electrical effects. We corroborate these simulations
with data from electrical test structures specifically targeted to elucidate these effects.
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