Variability aware interconnect timing models for double patterning

Eric Y. Chin; Andrew R. Neureuther

doi:10.1117/12.814281

12 March 2009 Variability aware interconnect timing models for double patterning

Eric Y. Chin, Andrew R. Neureuther

Proceedings Volume 7275, Design for Manufacturability through Design-Process Integration III; 727513 (2009) https://doi.org/10.1117/12.814281
Event: SPIE Advanced Lithography, 2009, San Jose, California, United States

Abstract

A compact model for estimating delay variations due to double patterning lithography process variations on interconnect layers is presented. Through process simulation and circuit analysis of one-dimensional interconnect topologies, the delay response from focus, exposure, and overlay is studied. Using a process window defined by 10% linewidth change from focus and exposure, and ±10% overlay error, a worst case change in delay of 3.9% is observed for an optimal buffer circuit. It is shown that such delay responses can be modeled using a second order polynomial function of process parameters. The impact of multiple interconnect variations in unique layout environments is studied using multiple segments of interconnects each experiencing different variations. The overall delay responses are then examined, and it is shown that for these layout structures, the separate variations combine in a manner that is both additive and subtractive, thereby reducing the overall delay variations.

Citation Download Citation

Eric Y. Chin and Andrew R. Neureuther "Variability aware interconnect timing models for double patterning", Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 727513 (12 March 2009); https://doi.org/10.1117/12.814281

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