Paper
12 March 2009 Convergent automated chip level lithography checking and fixing at 45nm
Valerio Perez, Shyue Fong Quek, Sky Yeo, Colin Hui, Kuang Kuo Lin, Walter Ng, Michel Cote, Bala Kasthuri, Philippe Hurat, Matt A. Thompson, Chi-Min Yuan, Puneet Sharma
Author Affiliations +
Abstract
To provide fabless designers the same advantage as Integrated Device Manufacturer (IDMs), a design-oriented litho model has been calibrated and an automated lithography (litho) hotspot detection and fixing flow has been implemented during final routing optimization. This paper shows how a design-oriented litho model was built and used to automate a litho hotspot fixing design flow. The model, calibrated and validated against post-OPC contour data at 99%, was embedded into a Litho Physical Analyzer (LPA) tech file. It allowed the litho contour of drawn layouts to be simulated at full chip level to detect litho hotspots and to provide fixing guidelines. Automated hotspots fixing was hence made possible by feeding the guidelines to the fixing tools in an industry based integrated flow. Post-fixing incremental checks were also performed to converge to a clean design.
© (2009) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Valerio Perez, Shyue Fong Quek, Sky Yeo, Colin Hui, Kuang Kuo Lin, Walter Ng, Michel Cote, Bala Kasthuri, Philippe Hurat, Matt A. Thompson, Chi-Min Yuan, and Puneet Sharma "Convergent automated chip level lithography checking and fixing at 45nm", Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 72751S (12 March 2009); https://doi.org/10.1117/12.816593
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CITATIONS
Cited by 2 scholarly publications.
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KEYWORDS
Calibration

Lithography

Optical proximity correction

Critical dimension metrology

Silicon

Data modeling

Manufacturing

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