ESL flow for a hardware H.264/AVC decoder using TLM-2.0 and high level synthesis: a quantitative study

M. Thadani; P. P. Carballo; P. Hernández; G. Marrero; A. Núñez

doi:10.1117/12.821647

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28 May 2009 ESL flow for a hardware H.264/AVC decoder using TLM-2.0 and high level synthesis: a quantitative study

M. Thadani, P. P. Carballo, P. Hernández, G. Marrero, A. Núñez

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Proceedings Volume 7363, VLSI Circuits and Systems IV; 73630K (2009) https://doi.org/10.1117/12.821647
Event: SPIE Europe Microtechnologies for the New Millennium, 2009, Dresden, Germany

Abstract

The present paper describes an Electronic System Level (ESL) design methodology which was established and employed in the creation of a H.264/AVC baseline decoder. The methodology involves the synthesis of the algorithmic description of the functional blocks that comprise the decoder, using a high level synthesis tool. Optimization and design space exploration is carried out at the algorithmic level before performing logic synthesis. Final, post-place and route implementation results show that the decoder can operate at the target frequency of 100 MHz and meet real time requirements for QCIF frames.

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M. Thadani, P. P. Carballo, P. Hernández, G. Marrero, and A. Núñez "ESL flow for a hardware H.264/AVC decoder using TLM-2.0 and high level synthesis: a quantitative study", Proc. SPIE 7363, VLSI Circuits and Systems IV, 73630K (28 May 2009); https://doi.org/10.1117/12.821647

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