Static power dissipation in adder circuits: the UDSM domain

Steve Cayouette; Dhamin Al-Khalili

doi:10.1117/12.819798

28 May 2009 Static power dissipation in adder circuits: the UDSM domain

Steve Cayouette, Dhamin Al-Khalili

Proceedings Volume 7363, VLSI Circuits and Systems IV; 736311 (2009) https://doi.org/10.1117/12.819798
Event: SPIE Europe Microtechnologies for the New Millennium, 2009, Dresden, Germany

Abstract

This paper presents adder circuits of various architectures aimed at reducing static power dissipation. Circuit topologies for basic building blocks were evaluated for fabrication technologies of 65nm down to 32nm, and simulation results are presented. This work has lead to the development of various low power adder circuits and provides comparative analysis leading to the recommendation that a variable size block carry select adder is the best performer, taking into consideration both static and dynamic power dissipation.

Citation Download Citation

Steve Cayouette and Dhamin Al-Khalili "Static power dissipation in adder circuits: the UDSM domain", Proc. SPIE 7363, VLSI Circuits and Systems IV, 736311 (28 May 2009); https://doi.org/10.1117/12.819798

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available