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11 May 2009In-die mask registration metrology for 32nm node DPT lithography
Pattern placement on reticles is considered a key performance issue for Double Patterning Lithography (DPL) for the
32nm node and beyond. Pattern placement metrology on reticles may therefore become an important yield enabling
factor for 32nm node semiconductor device manufacturing. Today in the case of logic designs, mask metrology is
performed on dedicated registration test patterns in the kerf area between active dies, or on metrology cells inside the
active array. However, with the introduction of DPL, the overlay requirements will become more stringent and therefore
reticles need to be characterized in greater detail. In order to achieve the tighter overlay performance targets of less than
7nm [1] on the wafer for the 32nm node, registration metrology on the mask is expected to include "active" structures in
the die. These structures may not have parallel edges and thus standard edge detection algorithms for registration
metrology may not be applicable. We will explain the measurement principle and report on the first measurement results
obtained on from the actual state-of-the-art registration metrology tool on test reticles simulating metrology in the dense
active array. These data will be analyzed and compared with results achieved using standard registration pattern. Data
evaluation software algorithms are already available to compare pattern placement performance between reticle layers.
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Klaus-Dieter Roeth, Frank Laske, Michael Heiden, Dieter Adam, Artur Boesser, Klaus Rinn, André Schepp, Jochen Bender, "In-die mask registration metrology for 32nm node DPT lithography," Proc. SPIE 7379, Photomask and Next-Generation Lithography Mask Technology XVI, 737915 (11 May 2009); https://doi.org/10.1117/12.824282