Design And Performance Of A 10 MIP Optoelectronic Central Processing Unit

R. Arrathoon; S. Kozaitis

doi:10.1117/12.939907

11 August 1987 Design And Performance Of A 10 MIP Optoelectronic Central Processing Unit

R. Arrathoon, S. Kozaitis

Proceedings Volume 0752, Digital Optical Computing; (1987) https://doi.org/10.1117/12.939907
Event: OE LASE'87 and EO Imaging Symposium, 1987, Los Angeles, CA, United States

Abstract

A description of a massively parallel optoelectronic CPU is presented. Integral to the design of the device is a complex fiberoptic interconnection pattern that serves as a portion of a programmable logic array. A rudimentary instruction set for this CPU is presented, and a corresponding interconnection pattern is derived. The system architecture is examined, and a physical realization of the CPU is presented. Operating characteristics at ten million instructions per second are detailed.

Citation Download Citation

R. Arrathoon and S. Kozaitis "Design And Performance Of A 10 MIP Optoelectronic Central Processing Unit", Proc. SPIE 0752, Digital Optical Computing, (11 August 1987); https://doi.org/10.1117/12.939907

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