Source mask optimization (SMO) at full chip scale using inverse lithography technology (ILT) based on level set methods

Linyong Pang; Peter Hu; Danping Peng; Dongxue Chen; Tom Cecil; Lin He; Guangming Xiao; Vikram Tolani; Thuc Dam; Ki-Ho Baik; Bob Gleason

doi:10.1117/12.843578

12 December 2009 Source mask optimization (SMO) at full chip scale using inverse lithography technology (ILT) based on level set methods

Linyong Pang, Peter Hu, Danping Peng, Dongxue Chen, Tom Cecil, Lin He, Guangming Xiao, Vikram Tolani, Thuc Dam, Ki-Ho Baik, Bob Gleason

Author Affiliations +

Proceedings Volume 7520, Lithography Asia 2009; 75200X (2009) https://doi.org/10.1117/12.843578
Event: SPIE Lithography Asia, 2009, Taipei, Taiwan

Abstract

For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents a great challenge, because it is fundamentally constrained by basic principles of optical physics. For years, source optimization and mask pattern correction have been conducted as two separate RET steps. For source optimization, the source was optimized based on fixed mask patterns; in other words, OPC and SRAFs were not considered during source optimization. Recently, some new approaches to Source Mask Optimization (SMO) have been introduced for the lithography development stage. The next important step would be the extension of SMO, and in particular the mask optimization in SMO, into full chip. In this paper, a computational framework based on Level Set Method is presented that enables simultaneous source and mask optimization (using Inverse Lithography Technology, or ILT), and can extend the SMO from single clip, to multiple clips, all the way to full chip. Memory and logic device results at the 32nm node and below are presented which demonstrate the benefits of this level-set-method-based SMO and its extendibility to full chip designs.

Citation Download Citation

Linyong Pang, Peter Hu, Danping Peng, Dongxue Chen, Tom Cecil, Lin He, Guangming Xiao, Vikram Tolani, Thuc Dam, Ki-Ho Baik, and Bob Gleason "Source mask optimization (SMO) at full chip scale using inverse lithography technology (ILT) based on level set methods", Proc. SPIE 7520, Lithography Asia 2009, 75200X (12 December 2009); https://doi.org/10.1117/12.843578

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available