Self-aligned maskless process for etching cavities in SOI wafers to enhance the quality factor of MEMS resonators

Wajihuddin Mohammad; Ville Kaajakari

doi:10.1117/12.843078

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4 February 2010 Self-aligned maskless process for etching cavities in SOI wafers to enhance the quality factor of MEMS resonators

Wajihuddin Mohammad, Ville Kaajakari

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Proceedings Volume 7592, Reliability, Packaging, Testing, and Characterization of MEMS/MOEMS and Nanodevices IX; 75920U (2010) https://doi.org/10.1117/12.843078
Event: SPIE MOEMS-MEMS, 2010, San Francisco, California, United States

Abstract

We present a low cost, self-aligned, process to etch cavities under movable structures in commercially available SOI wafers. The cavity is formed by electrochemically etching the substrate through the openings in the SOI structural layer. A tuning fork structure fabricated with the cavity SOI process has resonant frequency of 247 kHz and the measured intrinsic is Q = 82,000 at 35 mTorr. Comparing the measured quality factor as function of pressure for devices with and without the cavity, the devices with cavity showed a consistent improvement in the quality factor by a factor of 2-3 except for very low pressures where the intrinsic mechanical quality factor dominates. As the distance between the device and substrate is increased from 2 μm (buried oxide thickness) to 10 μm (electrochemically etched cavity), the parasitic capacitance to the substrate is also reduced by 5x. In addition, the stiction between the device and substrate is effectively eliminated.

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Wajihuddin Mohammad and Ville Kaajakari "Self-aligned maskless process for etching cavities in SOI wafers to enhance the quality factor of MEMS resonators", Proc. SPIE 7592, Reliability, Packaging, Testing, and Characterization of MEMS/MOEMS and Nanodevices IX, 75920U (4 February 2010); https://doi.org/10.1117/12.843078

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