Paper
25 February 2010 Serial pixel analog-to-digital converter (ADC)
Author Affiliations +
Proceedings Volume 7598, Optical Components and Materials VII; 75980V (2010) https://doi.org/10.1117/12.845801
Event: SPIE OPTO, 2010, San Francisco, California, United States
Abstract
This method reduces the data path from the counter to the pixel register of the analog-to-digital converter (ADC) from as many as 10 bits to a single bit. The reduction in data path width is accomplished by using a coded serial data stream similar to a pseudo random number (PRN) generator. The resulting encoded pixel data is then decoded into a standard hexadecimal format before storage. The high-speed serial pixel ADC concept is based on the single-slope integrating pixel ADC architecture. Previous work has described a massively parallel pixel readout of a similar architecture. The serial ADC connection is similar to the state-of-the art method with the exception that the pixel ADC register is a shift register and the data path is a single bit. A state-of-the-art individual-pixel ADC uses a single-slope charge integration converter architecture with integral registers and "one-hot" counters. This implies that parallel data bits are routed among the counter and the individual on-chip pixel ADC registers. The data path bit-width to the pixel is therefore equivalent to the pixel ADC bit resolution.
© (2010) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Eric D. Larson "Serial pixel analog-to-digital converter (ADC)", Proc. SPIE 7598, Optical Components and Materials VII, 75980V (25 February 2010); https://doi.org/10.1117/12.845801
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KEYWORDS
Clocks

Logic

Analog electronics

Prototyping

Capacitors

Data conversion

Image resolution

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