Translator Disclaimer
Paper
20 March 2010 Full chip correction of EUV design
Author Affiliations +
Abstract
Extreme Ultraviolet Lithography (EUVL) is currently the most promising technology for advanced manufacturing nodes: it recently demonstrated the feasibility of 32nm and 22nm node devices, and pre-production tools are expected to be delivered by 2010. Generally speaking, EUVL is less in need of Optical Proximity Correction (OPC) as compared to 193nm lithography, and the device feasibility studies were indeed carried out with limited or no correction. However, a rigorous optical correction strategy and an appropriate Electronic Design Automation (EDA) infrastructure is critical to face the challenges of the 22nm node and beyond, and EUV-specific effects such as flare and shadowing have to be fully integrated in the correction flow and properly tested. This study aims to assess in detail the quality of a full chip optical correction for a EUV design, as well to discuss the available approaches to compensate for EUV-specific effects. Extensive data sets have been collected on the ASML EUV Alpha-Demo Tool (ADT) using the latest IMEC baseline resist Shin-Etsu SEVR59. In total about 1300 CD measurements at wafer level and 700 at mask level were used as input for model calibration and validation. The smallest feature size in the data set was 32nm. Both one-dimensional and two-dimensional structures through CD and pitch were measured. The mask used in this calibration exercise allowed the authors to modulate flare by varying tiling densities within the range expected in the final design. The OPC model was fitted and validated against the CD data collected on the EUV ADT. The shadowing effect was modeled by means of a single bias correction throughout the design. Horizontal and vertical features of different type through pitch and CD were used to calibrate the shadowing correction, and the extent of the validity of the single bias approach is discussed. In addition, the quality of the generated full-chip flare maps has been tested against experimental results, and the model has been validated in the full flare range available within the mask. The model calibration yielded an RMS of about 1nm, and a EUV mask fully corrected for OPC, flare and shadowing was finally fabricated and qualified.
© (2010) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
G. F. Lorusso, E. Hendrickx, G. L. Fenger, and A. Niroomand "Full chip correction of EUV design", Proc. SPIE 7636, Extreme Ultraviolet (EUV) Lithography, 763615 (20 March 2010); https://doi.org/10.1117/12.846966
PROCEEDINGS
10 PAGES


SHARE
Advertisement
Advertisement
RELATED CONTENT

EUV OPC modeling and correction requirements
Proceedings of SPIE (March 18 2014)
Compact 2D OPC modeling of a metal oxide EUV resist...
Proceedings of SPIE (March 27 2017)
OPC model building for EUV lithography
Proceedings of SPIE (September 26 2019)
Model calibration and validation for pre-production EUVL
Proceedings of SPIE (March 23 2012)
Accurate models for EUV lithography
Proceedings of SPIE (September 23 2009)

Back to Top