Full area pattern decomposition of self-aligned double patterning for 30nm node NAND FLASH process

Yi-Shiang Chang; Jason Sweis; Jun-Cheng Lai; Chia-Chi Lin; Jonathan Yu

doi:10.1117/12.845831

2 April 2010 Full area pattern decomposition of self-aligned double patterning for 30nm node NAND FLASH process

Yi-Shiang Chang, Jason Sweis, Jun-Cheng Lai, Chia-Chi Lin, Jonathan Yu

Proceedings Volume 7637, Alternative Lithographic Technologies II; 76371N (2010) https://doi.org/10.1117/12.845831
Event: SPIE Advanced Lithography, 2010, San Jose, California, United States

Abstract

Self Aligned Double Patterning (SADP) has the advantage of dense array definition with good pitch control and is hence useful for memory devices; but its feasibility of two-dimensional circuit patterns definition is restricted on the other hand. In SPIE 2009, we had proposed the ideas of 30nm node NAND FLASH cell circuit critical feature (pickup, gate, contact array) decomposition by SADP, based on manual design. The concerns of process integration as well as SADP alignment algorithm for each mask step were investigated and countermeasures were presented. In this paper, the previous works on manual-based pattern decomposition are extended to a more sophisticated use on full-area NAND FLASH critical layer layout decomposition by utilizing an automated electronic design (EDA) tool. The decomposition tool together with OPC and simulation tools are integrated to optimize the lithographic performance of local critical patterns in each decomposed mask step, and comparisons have been made as well to investigate the differences in layout splitting algorithm between EDA-based and manual-based decomposition. Finally, the full-area (9350×12800um) layout decomposition has been successfully demonstrated on NAND FLASH Gate and Metal critical layers by using the EDA tool with improved 2D structure handling algorithms.

Citation Download Citation

Yi-Shiang Chang, Jason Sweis, Jun-Cheng Lai, Chia-Chi Lin, and Jonathan Yu "Full area pattern decomposition of self-aligned double patterning for 30nm node NAND FLASH process", Proc. SPIE 7637, Alternative Lithographic Technologies II, 76371N (2 April 2010); https://doi.org/10.1117/12.845831

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