Nanoimprint template fabrication using wafer pattern for sub-30nm

C. M. Park; K. J. Kim; Y. J. Lee; K. Y. Cho; Y. M. Lee; J. O. Park; In S. Kim; J. H. Yeo; S. W. Choi; C. H. Park; D. H. Lee; B. K. Lee; S. W. Hwang

doi:10.1117/12.846481

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2 April 2010 Nanoimprint template fabrication using wafer pattern for sub-30nm

C. M. Park, K. J. Kim, Y. J. Lee, K. Y. Cho, Y. M. Lee, J. O. Park, In S. Kim, J. H. Yeo, S. W. Choi, C. H. Park, D. H. Lee, B. K. Lee, S. W. Hwang

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Proceedings Volume 7637, Alternative Lithographic Technologies II; 76371R (2010) https://doi.org/10.1117/12.846481
Event: SPIE Advanced Lithography, 2010, San Jose, California, United States

Abstract

Patterning of sub-30 nm features using high resolution nano-imprint lithography (NIL) requires use of quartz templates. To this end, various fabrication methods such as e-beam lithography, edge lithography, and focused ion beam lithography were employed for the template formation. Despite significant advances using these methods, NIL template formation process suffers from low throughput and high cost of fabrication when compared with the fabrication of masks used in optical lithography. This is largely owing to a 4X difference in feature sizes involved for the fabrication of NIL template and optical lithography mask. In this paper, we report on a simple, cost-effective method for the fabrication of sub-30 nm NIL templates. Typical fabrication-time required for the formation of sub-30 nm HP templates using conventional Gaussian beam electron beam lithography, runs into several days. Additionally, complicated etch procedures must be employed for pattern transfer onto quartz substrates. Here we propose a low cost, simplified fabrication process for the formation of high resolution NIL templates using wafer pattern replication. We fabricated sub- 30nmHP poly-silicon lines and spaces on silicon wafer using multiple patterning technique. These patterns were subsequently transferred onto quartz substrates using NIL technique. Several types of features were studied to realize a template using the triple patterning technique described above. Results of wafer printing using the said template will be discussed.

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C. M. Park, K. J. Kim, Y. J. Lee, K. Y. Cho, Y. M. Lee, J. O. Park, In S. Kim, J. H. Yeo, S. W. Choi, C. H. Park, D. H. Lee, B. K. Lee, and S. W. Hwang "Nanoimprint template fabrication using wafer pattern for sub-30nm", Proc. SPIE 7637, Alternative Lithographic Technologies II, 76371R (2 April 2010); https://doi.org/10.1117/12.846481

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