Automated optimized overlay sampling for high-order processing in double patterning lithography

Chiew-seng Koay; Matthew E. Colburn; Pavel Izikson; John C. Robinson; Cindy Kato; Hiroyuki Kurita; Venkat Nagaswami

doi:10.1117/12.846371

1 April 2010 Automated optimized overlay sampling for high-order processing in double patterning lithography

Chiew-seng Koay, Matthew E. Colburn, Pavel Izikson, John C. Robinson, Cindy Kato, Hiroyuki Kurita, Venkat Nagaswami

Proceedings Volume 7638, Metrology, Inspection, and Process Control for Microlithography XXIV; 76381R (2010) https://doi.org/10.1117/12.846371
Event: SPIE Advanced Lithography, 2010, San Jose, California, United States

Abstract

A primary concern when selecting an overlay sampling plan is the balance between accuracy and throughput. Two significant inflections in the semiconductor industry require even more careful sampling consideration: the transition from linear to high order overlay control, and the transition to dual patterning lithography (DPL) processes. To address the sampling challenges, an analysis tool in KT-Analyzer has been developed to enable quantitative evaluation of sampling schemes for both stage-grid and within-field analysis. Our previous studies indicated (1) the need for fully automated solutions that takes individual interpretation from the optimization process, and (2) the need for improved algorithms for this automation; both of which are described here.

Citation Download Citation

Chiew-seng Koay, Matthew E. Colburn, Pavel Izikson, John C. Robinson, Cindy Kato, Hiroyuki Kurita, and Venkat Nagaswami "Automated optimized overlay sampling for high-order processing in double patterning lithography", Proc. SPIE 7638, Metrology, Inspection, and Process Control for Microlithography XXIV, 76381R (1 April 2010); https://doi.org/10.1117/12.846371

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