The evolution of patterning process models in computational lithography

John L. Sturtevant

doi:10.1117/12.851816

12 March 2010 The evolution of patterning process models in computational lithography

John L. Sturtevant

Proceedings Volume 7639, Advances in Resist Materials and Processing Technology XXVII; 763902 (2010) https://doi.org/10.1117/12.851816
Event: SPIE Advanced Lithography, 2010, San Jose, California, United States

Abstract

Thirty five years have passed since the first lithography process models were presented, and since that time there has been remarkable progress in the predictive power, performance, and applicability of these models in addressing many different challenges within the semiconductor industry. The impact has been profound, and this paper will attempt to highlight some of the key contributions which have been made, particularly as patterning simulation has moved beyond the realm of process development to full chip production enablement. In addition, this paper will outline the new process simulation challenges which emerge as the industry approaches sub-0.25 k₁ patterning. These challenges lie principally in driving towards ever improved accuracy for an expanding set of processes and failure modes, while maintaining or improving full chip data preparation cycle times.

Citation Download Citation

John L. Sturtevant "The evolution of patterning process models in computational lithography", Proc. SPIE 7639, Advances in Resist Materials and Processing Technology XXVII, 763902 (12 March 2010); https://doi.org/10.1117/12.851816

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