Paper
12 March 2010 Mask enhancer technology for sub-100nm pitch random logic layout contact hole fabrication
Takashi Yuito, Hiroshi Sakaue, Takashi Matsuda, Tadami Shimizu, Shigeo Irie, Fumio Iwamoto, Akio Misaka, Taichi Koizumi, Masaru Sasago
Author Affiliations +
Abstract
We have proposed a new resolution enhancement technology using attenuated mask with phase shifting aperture, named "Mask Enhancer", for random-logic contact hole pattern printing. In this study, we apply Mask Enhancer on sub-100nm pitch contact hole printing with 1.35NA ArF immersion lithography tool, and ensure that Mask Enhancer can improve MEEF at resolution limit and DOF at semi-dense and isolated pitch region. We demonstrate printing a fine 100nm pitch line of contacts and isolated simultaneously with MEEF of less than 4 by using Mask Enhancer and prove that Mask Enhancer is one of the most effective solutions for random logic layout contact hole fabrication for 28nm node and below.
© (2010) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Takashi Yuito, Hiroshi Sakaue, Takashi Matsuda, Tadami Shimizu, Shigeo Irie, Fumio Iwamoto, Akio Misaka, Taichi Koizumi, and Masaru Sasago "Mask enhancer technology for sub-100nm pitch random logic layout contact hole fabrication", Proc. SPIE 7640, Optical Microlithography XXIII, 76401B (12 March 2010); https://doi.org/10.1117/12.848025
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KEYWORDS
Photomasks

Printing

Lithography

Image enhancement

Logic

Transmittance

Lab on a chip

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