Compact low-cost high-sensitivity CMOS radar-on-chip integration for security applications

Changzhi Li; Jenshan Lin

doi:10.1117/12.848519

26 April 2010 Compact low-cost high-sensitivity CMOS radar-on-chip integration for security applications

Changzhi Li, Jenshan Lin

Proceedings Volume 7669, Radar Sensor Technology XIV; 76690N (2010) https://doi.org/10.1117/12.848519
Event: SPIE Defense, Security, and Sensing, 2010, Orlando, Florida, United States

Abstract

Based on the measurement results of a 5 GHz CMOS radar microchip, it is shown that low power CMOS radar-on-chip integration can have high detection sensitivity despite the large flicker noise and phase noise contributions around the signal of interest. Key technologies to further increase the detection sensitivity will be discussed, including software configured DC offset calibration, noise suppression using tunable baseband bandwidth limiter, and special receiver architecture for flicker noise reduction. The applications of low-cost high-sensitivity on-chip radar will be focused on surveillance and reconnaissance, sensing through-wall radar, ground penetration radar, border monitoring, and moving target detection.

Citation Download Citation

Changzhi Li and Jenshan Lin "Compact low-cost high-sensitivity CMOS radar-on-chip integration for security applications", Proc. SPIE 7669, Radar Sensor Technology XIV, 76690N (26 April 2010); https://doi.org/10.1117/12.848519

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