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13 May 2010 A 3D chip architecture for optical sensing and concurrent processing
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This paper presents an architecture for the implementation of vision chips in 3-D integration technologies. This architecture employs the multi-functional pixel concept to achieve full parallel processing of the information and hence high processing speed. The top layer includes an array of optical sensors which are parallel-connected to the second layer, consisting of an array of mixed-signal read-out and pre-processing cells. Multiplexing is employed so that each mixedsignal cell handles several optical sensors. The two remaining layer are respectively a memory (used to store different multi-scale images obtained at the mixed-signal layer) and an array of digital processors. A prototype of this architecture has been implemented in a FDSOI CMOS-3D technology with Through-Silicon-Vias of 5μm x 5μm pitch.
© (2010) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Ángel Rodríguez-Vázquez, Ricardo Carmona, Carlos Domínguez Matas, Manuel Suárez-Cambre, Victor Brea, Francisco Pozas, Gustavo Liñán, Peter Foldessy, Akos Zarandy, and Csaba Rekeczky "A 3D chip architecture for optical sensing and concurrent processing", Proc. SPIE 7726, Optical Sensing and Detection, 772613 (13 May 2010);


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