Low Voltage Sem Metrology For Pilot Line Applications

T. Ahmed; S-R. Chen; H. M. Naguib; T. A. Brunner; S. M. Stuber

doi:10.1117/12.940414

17 April 1987 Low Voltage Sem Metrology For Pilot Line Applications

T. Ahmed, S-R. Chen, H. M. Naguib, T. A. Brunner, S. M. Stuber

Proceedings Volume 0775, Integrated Circuit Metrology, Inspection, & Process Control; (1987) https://doi.org/10.1117/12.940414
Event: Microlithography Conferences, 1987, Santa Clara, CA, United States

Abstract

In this paper, we consider the application of low voltage scanning electron microscopy (SEM) to practical pilot line problems of critical dimension (CD) measurements and in-process wafer inspection of small geometry ( <2 pm) VLSI circuits . Two low voltage field emission CD measurement SEMs with automated wafer stages and computerized digital control CD systems were used. CD data from the SEM was compared with results from optical microscopy and electron probe metrology systems. Cross-calibration of CD data between the two SEMs was also analyzed using a variety of patterned layers. These included CD patterns measured after resist development and after etching of diffusion, poly Si gate, contact and metal layers in a 1.2 μm CMOS process. Examples of inprocess wafer inspection are presented. In addition, new applications of SEM metrology for sidewall spacer width and stepped contact CD measurements are demonstrated.

Citation Download Citation

T. Ahmed, S-R. Chen, H. M. Naguib, T. A. Brunner, and S. M. Stuber "Low Voltage Sem Metrology For Pilot Line Applications", Proc. SPIE 0775, Integrated Circuit Metrology, Inspection, & Process Control, (17 April 1987); https://doi.org/10.1117/12.940414

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