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16 February 2011 Optimizing quantum efficiency in a stacked CMOS sensor
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Proceedings Volume 7875, Sensors, Cameras, and Systems for Industrial, Scientific, and Consumer Applications XII; 787505 (2011)
Event: IS&T/SPIE Electronic Imaging, 2011, San Francisco Airport, California, United States
Optimizing quantum efficiency of image sensors, whether CCD or CMOS, has usually required backside thinning to bring the photon receiving surface close to the charge generation elements. A new CMOS sensor architecture has been developed that permits high-fill-factor photodiodes to be placed at the silicon surface without the need for backside thinning. The photodiode access provided by this architecture permits application of highly-effective anti-reflection coatings on the input surface and construction of a mirror inside the silicon below the photodiodes to effectively double the optical thickness of the silicon charge generation volume. Secondary benefits of this architecture include prevention of light from reaching the CMOS circuitry under the photodiodes, improvement of near-infrared quantum efficiency, and reduction in optical artifacts caused by reflections from the sensor surface. Utilizing these techniques, a sensor is being constructed with 4096 x 4096 pixels 4.8 μm square with 95% fill factor backed by a mirror tuned to the 400-700 nm visible band and a front-surface anti-reflectance coating. The quantum efficiency is expected to exceed 80% through the visible and the global shutter extinction ratio should exceed 106:1. The sensors have been fabricated and first test data is due in February 2011.
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Rob Hannebauer, Sang Keun Yoo, David L. Gilblom, and Alexander D. Gilblom "Optimizing quantum efficiency in a stacked CMOS sensor", Proc. SPIE 7875, Sensors, Cameras, and Systems for Industrial, Scientific, and Consumer Applications XII, 787505 (16 February 2011);

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