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20 April 2011 Process solutions for reducing PR residue over non-planar wafer
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SAS (Self-Aligned Source) process has been widely adopted on manufacturing NOR Flash devices. To form the SAS structure, the compromise between small space patterning and sufficiently removing photo resist residue in topographical substrate has been a critical challenge as the device scaling down. In this study, photo simulation, layout optimization, resist processing and tri-layer materials were evaluated to form defect-free and highly extendible SAS structure for NOR Flash devices. Photo simulation suggested more coherent light source allowed the incident light to reach the trench bottom that facilitates the removal of photo resist. Mask bias also benefited the process latitude extension for residue-free SAS printing. In the photo resist processing, both lowering the SB (Soft Bake) and raising PEB (Post-Exposure Bake) temperature of photo resist were helpful to broaden the process window but the final pattern profile was not good enough. Thermal flow for pos-exposure pattern shrinkage achieved small CD (Critical Dimension) patterning with residue-free, however the materials loading effect is another issue to be addressed at memory array boundary. Tri-layer scheme demonstrated good results in terms of free from residue, better substrate reflectivity control, enabling smaller space printing to loosen overlay specification and minimizing the poly gate clipping defect. It was finally proposed to combine with etch effort to from the SAS structure. Besides it is also promising to extend to even smaller technology nodes.
© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
C. H. Lin, C. H. Huang, Elvis Yang, T. H. Yang, K. C. Chen, and Chih-Yuan Lu "Process solutions for reducing PR residue over non-planar wafer", Proc. SPIE 7971, Metrology, Inspection, and Process Control for Microlithography XXV, 79712C (20 April 2011);


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