Novel approaches to implement the self-aligned spacer double-patterning process toward 11-nm node and beyond

Hidetami Yaegashi; Kenichi Oyama; Kazuo Yabe; Shohei Yamauchi; Arisa Hara; Sakurako Natori

doi:10.1117/12.878943

15 April 2011 Novel approaches to implement the self-aligned spacer double-patterning process toward 11-nm node and beyond

Hidetami Yaegashi, Kenichi Oyama, Kazuo Yabe, Shohei Yamauchi, Arisa Hara, Sakurako Natori

Author Affiliations +

Proceedings Volume 7972, Advances in Resist Materials and Processing Technology XXVIII; 79720B (2011) https://doi.org/10.1117/12.878943
Event: SPIE Advanced Lithography, 2011, San Jose, California, United States

Abstract

Historically, lithographic scaling has been driven by both improvements in wavelength and numerical aperture. In the semiconductor industry, the transition to 1.35NA immersion lithography has recently been completed, and the focus is now on double patterning techniques (DPT) as a means to circumvent the limitations of Rayleigh's definition. Actually, self-aligned spacer double patterning (SADP) has already been employed in high volume manufacturing of NAND flash memory devices. This paper introduces demonstration results focused on the extendibility of double patterning techniques for various device layouts.

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Hidetami Yaegashi, Kenichi Oyama, Kazuo Yabe, Shohei Yamauchi, Arisa Hara, and Sakurako Natori "Novel approaches to implement the self-aligned spacer double-patterning process toward 11-nm node and beyond", Proc. SPIE 7972, Advances in Resist Materials and Processing Technology XXVIII, 79720B (15 April 2011); https://doi.org/10.1117/12.878943

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