Paper
22 March 2011 Correcting image placement errors using registration control (RegC) technology
Author Affiliations +
Abstract
The 2009 ITRS update specifies wafer overlay control as one of the major tasks for the sub 40 nm nodes. Wafer overlay is strongly dependent on mask image placement error (registration errors or Reg errors)1 in addition to CD control and defect control. The specs for registration or mask placement accuracy are twice as difficult in some of the double patterning techniques (DPT). This puts a heavy challenge on mask manufacturers (mask shops) to comply with advanced node registration specifications. Registration test masks as well as production masks were measured on a standard registration tool and the registration error was calculated and plotted. A specially developed algorithm was used to compute a correction lateral strain field that would minimize the registration error. A laser based prototype RegCTM tool was used to generate a strain field which corrected for the pre measured registration errors. Finally the post registration error map was measured. The resulting residual registration error field with and without scale and orthogonal errors removed was calculated. In this paper we present first results of registration control experiments using the prototype RegCTM tool.
© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Erez Graitzer, Gunter Antesberger, Guy Ben-Zvi, Avi Cohen, Vladimir Dmitriev, and Stephanie Winkelmeier "Correcting image placement errors using registration control (RegC) technology", Proc. SPIE 7973, Optical Microlithography XXIV, 797312 (22 March 2011); https://doi.org/10.1117/12.879885
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CITATIONS
Cited by 5 scholarly publications and 5 patents.
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KEYWORDS
Photomasks

Image registration

Overlay metrology

Scanners

Metrology

Manufacturing

Semiconducting wafers

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