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5 April 2011 Physical simulation for verification and OPC on full chip level
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In this paper, we introduce a rigorous OPC technology that links the physical lithography simulation with the OPC. Firstly, the various aspects of the rigorous OPC, related to process flow, are discussed and the practical feasibility of the embedded rigorous verification is taken into account, which can make the rigorous treatment of the full-chip level possible without any additional manual efforts. We explain an embedded rigorous verification flow and the basic structure of its functionality. Finally, its practical application to real cases is discussed.
© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Seongbo Shim, Seongho Moon, Youngchang Kim, Seongwoon Choi, Younghee Kim, Bernd Küchler, Ulrich Klostermann, Munhoe Do, and Sooryoung Lee "Physical simulation for verification and OPC on full chip level", Proc. SPIE 7973, Optical Microlithography XXIV, 79732I (5 April 2011);


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