Physical simulation for verification and OPC on full chip level

Seongbo Shim; Seongho Moon; Youngchang Kim; Seongwoon Choi; Younghee Kim; Bernd Küchler; Ulrich Klostermann; Munhoe Do; Sooryoung Lee

doi:10.1117/12.879577

Translator Disclaimer

5 April 2011 Physical simulation for verification and OPC on full chip level

Seongbo Shim, Seongho Moon, Youngchang Kim, Seongwoon Choi, Younghee Kim, Bernd Küchler, Ulrich Klostermann, Munhoe Do, Sooryoung Lee

Author Affiliations +

Proceedings Volume 7973, Optical Microlithography XXIV; 79732I (2011) https://doi.org/10.1117/12.879577
Event: SPIE Advanced Lithography, 2011, San Jose, California, United States

Abstract

In this paper, we introduce a rigorous OPC technology that links the physical lithography simulation with the OPC. Firstly, the various aspects of the rigorous OPC, related to process flow, are discussed and the practical feasibility of the embedded rigorous verification is taken into account, which can make the rigorous treatment of the full-chip level possible without any additional manual efforts. We explain an embedded rigorous verification flow and the basic structure of its functionality. Finally, its practical application to real cases is discussed.

Citation Download Citation

Seongbo Shim, Seongho Moon, Youngchang Kim, Seongwoon Choi, Younghee Kim, Bernd Küchler, Ulrich Klostermann, Munhoe Do, and Sooryoung Lee "Physical simulation for verification and OPC on full chip level", Proc. SPIE 7973, Optical Microlithography XXIV, 79732I (5 April 2011); https://doi.org/10.1117/12.879577

ACCESS THE FULL ARTICLE