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23 March 2011Feasibility study on the mask compensation of gate CD non-uniformity
caused by etching process
It's well known that geometrical features of the chip layout influence the change in critical dimension during etch in
macroscopic and microscopic ways but how well those impact could be measured and compensated are still of concern.
In this paper, the former factor is trying to be translated in terms of local pattern density measured in a critical radius and
the latter one is in terms of distance to the nearest feature. The magnitude of each contribution has been measured for
gate process at 180 nm technology node. Increase in local pattern density accompanying the slow etch rate within a
certain critical radius results in more than 5 nm CD drop. An attempt to acquire more comprehensive data related to the
local pattern density has been made and the chip-scale compensation rule for the real application has been proposed
accordingly. Meanwhile, the rising trend of post-etch CD with the increase in distance to the nearest feature is
maintained until the distance reaches 12 μm, which is much larger than the optical distance recommended in the
photolithography-based OPC setup. The final post-etch CD variation caused by this short-ranged geometrical influence
is huge reaching 30 nm so that another challenge should be taken into consideration as the full compensation of the
difference will ask you to sacrifice the lithographic process margin.
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Wan Ho Kim, Ek Jen Yet, Siew Ing Yet, Boon Chun Lee, "Feasibility study on the mask compensation of gate CD non-uniformity caused by etching process," Proc. SPIE 7973, Optical Microlithography XXIV, 797331 (23 March 2011); https://doi.org/10.1117/12.879197