Paper
4 April 2011 Timing variability analysis for layout-dependent-effects in 28nm custom and standard cell-based designs
Author Affiliations +
Abstract
We identify most recent sources of transistor layout dependent effects (LDE) such as stress, lithography, and well proximity effects (WPE), and outline modeling and analysis methods for 28 nm. These methods apply to custom layout, standard cell designs, and context-aware post-route analysis. We show how IC design teams can use a model-based approach to quantify and analyze variability induced by LDE. We reduce the need for guard-bands that negate the performance advantages that stress brings to advanced process technologies.
© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Philippe Hurat, Rasit O. Topaloglu, Ramez Nachman, Piyush Pathak, Jac Condella, Sriram Madhavan, and Luigi Capodieci "Timing variability analysis for layout-dependent-effects in 28nm custom and standard cell-based designs", Proc. SPIE 7974, Design for Manufacturability through Design-Process Integration V, 797412 (4 April 2011); https://doi.org/10.1117/12.882508
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CITATIONS
Cited by 2 scholarly publications.
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KEYWORDS
Transistors

Lithography

Neodymium

Standards development

Data modeling

Silicon

Statistical analysis

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