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20 September 1976 Overlay Precision For Micron Lithography
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Abstract
Attention is directed to the need for pattern-to-pattern overlay precision commensurate with micron lithography for integrated circuit fabrication and an error target is suggested. Several sources of overlay error are identified, including: Position of pattern edges in processed layers Mask/wafer bending distortions Alignment mark detection Pattern generation, and Thermal expansion of masks and wafers Pattern replication The magnitude of parameter control needed to maintain the desired total precision is discussed for several cases. Individual errors need to be less than a few tenths of a pm for the total error objective to be met. Although this magnitude of error approaches the limits of optical measurement precision, the resulting circuit pattern can be adequately measured with vernier patterns. Reported achievements in E-Beam lithography show successful error containment for small fields. High precision overlay for full wafer exposure using masks will be significantly more difficult to achieve (e.g., in optical scanning cameras, photo-emissive E-Beam replicators, and X-ray proximity printers). However, there is justification for the effort in the increased wafers/unit time (thruput) that can be realized for lithographic tools using full wafer exposure.
© (1976) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
J. A. Underhill "Overlay Precision For Micron Lithography", Proc. SPIE 0080, Developments in Semiconductor Microlithography, (20 September 1976); https://doi.org/10.1117/12.954838
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