Parallel design patterns for a low-power, software-defined compressed video encoder

Michael W. Bruns; Martin A. Hunt; Durga Prasad; Nageswara Rao Gunupudi; Sekar Sonachalam

doi:10.1117/12.884422

26 May 2011 Parallel design patterns for a low-power, software-defined compressed video encoder

Michael W. Bruns, Martin A. Hunt, Durga Prasad, Nageswara Rao Gunupudi, Sekar Sonachalam

Proceedings Volume 8063, Mobile Multimedia/Image Processing, Security, and Applications 2011; 80630E (2011) https://doi.org/10.1117/12.884422
Event: SPIE Defense, Security, and Sensing, 2011, Orlando, Florida, United States

Abstract

Video compression algorithms such as H.264 offer much potential for parallel processing that is not always exploited by the technology of a particular implementation. Consumer mobile encoding devices often achieve real-time performance and low power consumption through parallel processing in Application Specific Integrated Circuit (ASIC) technology, but many other applications require a software-defined encoder. High quality compression features needed for some applications such as 10-bit sample depth or 4:2:2 chroma format often go beyond the capability of a typical consumer electronics device. An application may also need to efficiently combine compression with other functions such as noise reduction, image stabilization, real time clocks, GPS data, mission/ESD/user data or software-defined radio in a low power, field upgradable implementation. Low power, software-defined encoders may be implemented using a massively parallel memory-network processor array with 100 or more cores and distributed memory. The large number of processor elements allow the silicon device to operate more efficiently than conventional DSP or CPU technology. A dataflow programming methodology may be used to express all of the encoding processes including motion compensation, transform and quantization, and entropy coding. This is a declarative programming model in which the parallelism of the compression algorithm is expressed as a hierarchical graph of tasks with message communication. Data parallel and task parallel design patterns are supported without the need for explicit global synchronization control. An example is described of an H.264 encoder developed for a commercially available, massively parallel memorynetwork processor device.

Citation Download Citation

Michael W. Bruns, Martin A. Hunt, Durga Prasad, Nageswara Rao Gunupudi, and Sekar Sonachalam "Parallel design patterns for a low-power, software-defined compressed video encoder", Proc. SPIE 8063, Mobile Multimedia/Image Processing, Security, and Applications 2011, 80630E (26 May 2011); https://doi.org/10.1117/12.884422

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available

Members: $17.00

Non-members: $21.00 ADD TO CART

PROCEEDINGS
10 PAGES

DOWNLOAD PAPER SAVE TO MY LIBRARY

GET CITATION

RIGHTS & PERMISSIONS

Get copyright permission Get copyright permission on Copyright Marketplace

KEYWORDS

Computer programming

Data modeling

Video

Parallel processing

Parallel computing

Video compression

Clocks

Show All Keywords

Keywords/Phrases

Search In:

Publication Years