Translator Disclaimer
3 May 2011 Low-power, high-speed FFT processor for MB-OFDM UWB application
Author Affiliations +
Proceedings Volume 8067, VLSI Circuits and Systems V; 80670E (2011)
Event: SPIE Microtechnologies, 2011, Prague, Czech Republic
This paper presents a low-power, high-speed 4-data-path 128-point mixed-radix (radix-2 & radix-22) FFT processor for MB-OFDM Ultra-WideBand (UWB) systems. The processor employs the single-path delay feedback (SDF) pipelined structure for the proposed algorithm, it uses substructure-sharing multiplication units and shift-add structure other than traditional complex multipliers. Furthermore, the word lengths are properly chosen, thus the hardware costs and power consumption of the proposed FFT processor are efficiently reduced. The proposed FFT processor is verified and synthesized by using 0.13 μm CMOS technology with a supply voltage of 1.32 V. The implementation results indicate that the proposed 128-point mixed-radix FFT architecture supports a throughput rate of 1Gsample/s with lower power consumption in comparison to existing 128-point FFT architectures.
© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Guixuan Liang, Danping He, Eduardo de la Torre, and Teresa Riesgo "Low-power, high-speed FFT processor for MB-OFDM UWB application", Proc. SPIE 8067, VLSI Circuits and Systems V, 80670E (3 May 2011);

Back to Top