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13 October 2011 Yield optimization through MLR techniques
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Some chip manufacturing steps lead to non-negligible process variation at wafer level. Typically, chemomechanical planarization, known as CMP, is a nonhomogeneous process and thickness variations can be measured depending on the distance from a specific die to the wafer center. These variations have an impact on chip performances and thus on the final yield. This effect may be amplified by the fact that thickness variations on processed wafers introduce focus issues during later photo-lithography steps. Original chip layouts are modified by inserting dummies to correct thickness variation issues due to CMP, but these correction are based on models only depending on average values. In this paper, we propose a methodology to replace a single instance of the field written on the mask by multiple instances of this field as commonly used for Multi Layer Reticles. In the described methodology, each field of a same mask does not consist in different layers of the same chip, but of an optimized image of the same layer of the chip.
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Philippe Morey-Chaisemartin and Eric Beisser "Yield optimization through MLR techniques", Proc. SPIE 8166, Photomask Technology 2011, 81663H (13 October 2011);

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