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8 September 2011 Analysis and design of a low-noise ROIC for hybrid InGaAs infrared FPA
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The noises of CMOS readout integrated circuit (ROIC) for hybrid focal plane array (FPA) may occupy a great part of total noise in conditions that a low resistance or large capacitor detector interfacing with CTIA input stage. A novel low noise low power preamplifier with shared current-mirrors bias is designed. It has a gain of more than 90dB, which makes enough inject efficiency and low detector bias offset. Besides, it has strong detector bias control, because the shared current-mirror copies the DC current of the amplifier and generates the bias control voltage. A pixel level Correlated Double Sample circuits is designed in order to suppress the reset KTC noise and 1/f noise from preamplifier. An experimental chip of 30μm pitch 32×32 array was fabricated in standard 0.5μm CMOS mixed signal process. A few experimental structures are designed to study the allocating of layout area for low noise designing. The ROIC is bonded to an existing back-illuminated 30μm pitch InGaAs photodiode array with indium bump fabrication. The test of both the ROIC chips and InGaAs focal plane array is shown in this paper, and the contrast of different structure is shown and analyzed.
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Wei Zhang, SongLei Huang, ZhangCheng Huang, and Jiaxiong Fang "Analysis and design of a low-noise ROIC for hybrid InGaAs infrared FPA", Proc. SPIE 8193, International Symposium on Photoelectronic Detection and Imaging 2011: Advances in Infrared Imaging and Applications, 81933Q (8 September 2011);

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