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18 August 2011 A high-speed CMOS image sensor with column-parallel single capacitor CDSs and single-slope ADCs
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This paper presents a high speed CMOS image sensor (CIS) with column-parallel single capacitor correlated double samplings (CDSs), programmable gain amplifiers (PGAs) and single-slope analog-to-digital converters (ADCs). The single capacitor CDS circuit has only one capacitor so that the area CDS circuit is small. In order to attain appropriate image contrast under different light conditions, the signal range can be adjusted by PGA. Single-slope ADC has smaller chip area than others ADCs and is suitable for column-parallel CIS architectures. A prototype sensor of 256x256 pixels was realized in a 0.13μm 1P3M CIS process. Its pixel circuit is 4T active pixel sensor (APS) and pixel size is 10x10μm2. Total chip area is 4x4mm2. The prototype achieves the full frame rate in excess of 250 frames per second, the sensitivity of 10.7V/lx•s, the conversion gain of 55.6μV/e and the column-to- column fixed-pattern noise (FPN) 0.41%.
© (2011) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Quanliang Li, Cong Shi, and Nanjian Wu "A high-speed CMOS image sensor with column-parallel single capacitor CDSs and single-slope ADCs", Proc. SPIE 8194, International Symposium on Photoelectronic Detection and Imaging 2011: Advances in Imaging Detectors and Applications, 819433 (18 August 2011);


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