Translator Disclaimer
2 February 2012 Scaling CMOS photonics transceivers beyond 100 Gb/s
Author Affiliations +
Proceedings Volume 8265, Optoelectronic Integrated Circuits XIV; 82650A (2012)
Event: SPIE OPTO, 2012, San Francisco, California, United States
We report on the performance of an integrated four-channel parallel optical transceiver built in a CMOS photonics process, operating at 28 Gb/s per channel. The optical engine of the transceiver comprises a single silicon die and a hybrid integrated DFB laser. The silicon die contains the all functionalities needed for an optical transceiver: transmitter and receiver optics, electrical driver, receiver and control circuits. We also describe the CMOS photonics platform used to build such transceiver device, which consists of: an optically enabled CMOS process, a photonic device library, and a design infrastructure that is modeled after standard circuit design tools. We discuss how this platform can scale to higher speeds and channel counts.
© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.

Back to Top