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2 February 2012 Chip-scale demonstration of 3D integrated intrachip free-space optical interconnect
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Proceedings Volume 8265, Optoelectronic Integrated Circuits XIV; 82650C (2012)
Event: SPIE OPTO, 2012, San Francisco, California, United States
This paper presents the first chip-scale demonstration of an intra-chip free-space optical interconnect (FSOI) we recently proposed. This interconnect system uses point-to-point free-space optical links to construct an all-to-all intra-chip communication network. Unlike other electrical and waveguide-based optical interconnect systems, FSOI exhibits low latency, high energy efficiency, and large bandwidth density with little degradation for long distance transmission, and hence can significantly improve the performance of future many-core chips. A 1x1-cm2 chip prototype is fabricated on a germanium substrate with integrated photodetectors. A commercial 850-nm GaAs vertical-cavity-surface-emitting-laser (VCSEL) and fabricated fused silica micro-lenses are 3-D integrated on top of the germanium substrate. At a 1.4-cm distance, the measured optical transmission loss is 5 dB and crosstalk is less than -20 dB. The electrical-to-electrical bandwidth is 3.3 GHz, limited by the VCSEL.
© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Hui Wu, Berkehan Ciftcioglu, Rebecca Berman, Jiyanhun Hu, Shang Wang, Ioannis Savidis, Manish Jain, Duncan Moore, Michael Huang, Eby G. Friedman, and Gary Wicks "Chip-scale demonstration of 3D integrated intrachip free-space optical interconnect", Proc. SPIE 8265, Optoelectronic Integrated Circuits XIV, 82650C (2 February 2012);

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