Wafer level warpage characterization of 3D interconnect processing wafers

Po-Yi Chang; Yi-Sha Ku

doi:10.1117/12.916591

5 April 2012 Wafer level warpage characterization of 3D interconnect processing wafers

Po-Yi Chang, Yi-Sha Ku

Proceedings Volume 8324, Metrology, Inspection, and Process Control for Microlithography XXVI; 832415 (2012) https://doi.org/10.1117/12.916591
Event: SPIE Advanced Lithography, 2012, San Jose, California, United States

Abstract

We present a new metrology system based on a fringe reflection method for warpage characterizations during wafer thinning and temporary bonding processes. A set of periodic fringe patterns is projected onto the measuring wafer and the reflected fringe images are captured by a CCD camera. The fringe patterns are deformed due to the slope variation of the wafer surface. We demonstrate the use of phase-shit algorithms, the wafer surface slope variation and quantitative 3D surface profile even tiny dimples and dents on a wafer can be reconstructed. The experimental results show the warpages of the bonded wafer are below 20 μm after thinning down to the nominal thickness of 75 μm and 50 μm. The measurement precision is better than 2 um.

Citation Download Citation

Po-Yi Chang and Yi-Sha Ku "Wafer level warpage characterization of 3D interconnect processing wafers", Proc. SPIE 8324, Metrology, Inspection, and Process Control for Microlithography XXVI, 832415 (5 April 2012); https://doi.org/10.1117/12.916591

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