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The demand for ever shrinking semiconductor devices is driving efforts to reduce pattern dimensions in semiconductor
lithography. In this work, the aim is to find a single patterning litho solution for a 28nm technology node using 193nm
immersion lithography. Target poly pitch is 110nm and metal1 pitch is 90nm. For this, we have introduced a range of
different techniques to reach this goal. At this node, it becomes essential to include the layout itself into the optimization
process. This leads to the introduction of restricted design rules, together with the co-optimization of source and mask
(SMO) and the use of customized illumination modes (freeform illumination sources; FlexrayTM). Also, negative tone
development (NTD) is employed to further extend the applicability of 193nm immersion lithography. Traditionally, the
printing of contacts and trenches is done by using a dark field mask in combination with a positive tone resist and
positive tone development. The use of negative tone development enables images reversal. This allows benefiting from
the improved imaging performance when exposing with bright field masks. The same features can be printed in positive
tone resists and with improved process latitudes.
At the same time intermediate metal (IM) layers are used to connect the front-end and back-end-of-line, resulting in huge
area benefits compared to layouts without these IM layers. The use of these IM layers will not happen for the 28nm
node, but is intended to be introduced towards the 20nm node, and beyond. Nevertheless, the choice was made to use this
architecture to obtain a first learning cycle on this approach.
In this study, the use of negative tone development is explored, and its use for the various dark field critical layers in a
28nm node process is successfully demonstrated. In order to obtain sufficiently large process windows, structures are
printed larger than the designed target CD. As a consequence, a shrink of the structures needs to be applied to obtain the
target CD after etch. Different shrink approaches are compared. Final results on wafer are discussed, focusing on critical
layers as IM1, IM2, Via0 and Metal1.
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