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14 March 2012 Thickness-aware LFD for the hotspot detection induced by topology
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As a result, low fidelity patterns due to process variations can be detected and eventually corrected by designers as early in the tape out flow as right after design rule checking (DRC); a step no longer capable to totally account for process constraints anymore. This flow has proven to provide a more adequate level of accuracy when correlating systematic defects as seen on wafer with those identified through LFD simulations. However, at the 32nm and below, still distorted patterns caused by process variation are unavoidable. And, given the current state of the defect inspection metrology tools, these pattern failures are becoming more challenging to detect. In the framework of this paper, a methodology of advanced process window simulations with awareness of chip topology is presented. This method identifies the expected focal range different areas within a design would encounter due to different topology.
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Jae-Hyun Kang, Naya Ha, Joo-Hyun Park, Byung-Moo Kim, Seung Weon Paek, Hungbok Choi, Kee Sup Kim, Ahmed Mohy, Shady Abdelwahed, and Mohamed Imam "Thickness-aware LFD for the hotspot detection induced by topology", Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 83270P (14 March 2012);

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