Intra-cell process variability and compact modeling of LWR effects: from self-aligned multiple patterning to multiple-gate MOSFETs

Yijian Chen; Weiling Kang; Qi Cheng

doi:10.1117/12.916503

14 March 2012 Intra-cell process variability and compact modeling of LWR effects: from self-aligned multiple patterning to multiple-gate MOSFETs

Yijian Chen, Weiling Kang, Qi Cheng

Author Affiliations +

Proceedings Volume 8327, Design for Manufacturability through Design-Process Integration VI; 83270Z (2012) https://doi.org/10.1117/12.916503
Event: SPIE Advanced Lithography, 2012, San Jose, California, United States

Abstract

As promising paths to break the diffraction limit of optical lithography, several self-aligned multiple patterning (SAMP) techniques have been proposed to improve the resolution capability recently. In this paper, we show that SATP (selfaligned triple patterning) process variations differ significantly from conventional optical lithography process. It is found that mandrels fabricated by a SATP process usually come up with worse line-width roughness (LWR) and critical-dimension uniformity (CDU) than spacers do. In addition to that, the gap space between two neighboring spacers is often accompanied with a poor CDU. Similar to SATP process, the self-aligned quadruple patterning (SAQP) technique also brings its own characteristics of process variability along with the scaling capability. SAMP process variability (such as intra-cell variability and process multi-modality) and their impacts on device performance of the multiple-gate MOSFETs are discussed. Moreover, we develop an analytic double-gate MOSFET model to study the effects of LWR on both fin thickness and gate misalignment. Numerical simulations are carried out to verify the accuracy of our simplified model. This analytic approach provides an efficient method for compact modeling of LWR induced device variations.

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Yijian Chen, Weiling Kang, and Qi Cheng "Intra-cell process variability and compact modeling of LWR effects: from self-aligned multiple patterning to multiple-gate MOSFETs", Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 83270Z (14 March 2012); https://doi.org/10.1117/12.916503

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