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16 March 2012 Patterning of CMOS device structures for 40-80nm pitches and beyond
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CMOS device patterning for aggressively scaled pitches (smaller than 80nm pitch) faces many challenges. Maybe one of the most crucial issues during device formation is the pattern transfer from a soft mask (carbon based) material into a hard mask material. A very characteristic phenomenon is that mechanical failure of the soft material may be observed. While this was observed first for patterning below 80nm pitch, it becomes increasingly important for even smaller pitches (≤ 40 nm). Further process optimization by various pre- and post-treatments has enabled robust pattern transfer down to 40nm pitch. A systematic study of the parameters impacting this phenomenon will be shown. Other challenges for patterning devices include profile control and material loss during gate stack patterning and spacer formation. Lastly, initial patterning experiments at an even more aggressive pitch show that the mechanical failure previously observed for larger pitches once again becomes an increasingly important issue to consider.
© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
S. U. Engelmann, R. Martin, R. L. Bruce, H. Miyazoe, N. C. M. Fuller, W. S. Graham, E. M. Sikorski, M. Glodde, M. Brink, H. Tsai, J. Bucchignano, D. Klaus, E. Kratschmer, and M. A. Guillorn "Patterning of CMOS device structures for 40-80nm pitches and beyond", Proc. SPIE 8328, Advanced Etch Technology for Nanopatterning, 83280B (16 March 2012);

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