Optical Addressing Techniques For A Cmos Ram

W. H. Wu; L. A. Bergman; R. A. Allen; A. R. Johnston

doi:10.1117/12.967551

1 January 1987 Optical Addressing Techniques For A Cmos Ram

W. H. Wu, L. A. Bergman, R. A. Allen, A. R. Johnston

Proceedings Volume 0836, Optoelectronic Materials, Devices, Packaging, and Interconnects; (1987) https://doi.org/10.1117/12.967551
Event: Cambridge Symposium on Fiber Optics and Integrated Optoelectronics, 1987, Cambridge, MA, United States

Abstract

Progress on optically addressing a CMOS RAM for a feasibility demonstration of free space optical interconnection is reported in this paper. The optical RAM chip has been fabricated and functional testing is in progress. Initial results seem promising. New design and SPICE simulation of optical gate cell (OGC) circuits have been carried out to correct the slow fall time of the 'weak pull-down' OGC, which has been characterized experimentally and reported previously. Methods of reducing the response times of the photodiodes and the associated circuits are discussed. Even with the current photodiode, it appears that an OGC can be designed with a performance that is compatible with a CMOS circuit such as the RAM.

Citation Download Citation

W. H. Wu, L. A. Bergman, R. A. Allen, and A. R. Johnston "Optical Addressing Techniques For A Cmos Ram", Proc. SPIE 0836, Optoelectronic Materials, Devices, Packaging, and Interconnects, (1 January 1987); https://doi.org/10.1117/12.967551

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