Fama Architecture: Implementation Details

A. Alcolea; A. Martinez; P. Laguna; J. Navarro; T. Pollan; S. J, Vicente; A. Roy

doi:10.1117/12.943036

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19 October 1987 Fama Architecture: Implementation Details

A. Alcolea, A. Martinez, P. Laguna, J. Navarro, T. Pollan, S. J, Vicente, A. Roy

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Proceedings Volume 0856, IECON '87: Industrial Applications of Robotics & Machine Vision; (1987) https://doi.org/10.1117/12.943036
Event: IECON, Cambridge, 1987, Cambridge, MA, United States

Abstract

The FAMA (Fine granularity Advanced Multiprocessor Architecture), currently being developed in the Department of Electrical Engineering and Computer Science of the University of Zaragoza, is an SIMD array architecture optimized for computer-vision applications. Because of its high cost-effectiveness, it is a very interesting alternative for industrial systems. Papers describing the processor element of FAMA have been submitted to several conferences; this paper focuses on the rest of components that complete the architecture: controller, I/O interface and software. The controller generates instructions at a 10MHz rate, allowing efficient access to bidimensional data structures. The I/O interface is capable of reordering information for efficient I/O operations. Development tools and modules for classical computer-vision tasks are being worked on in a first stage, the implementation of models based on existing theories on human vision will follow.

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A. Alcolea, A. Martinez, P. Laguna, J. Navarro, T. Pollan, S. J, Vicente, and A. Roy "Fama Architecture: Implementation Details", Proc. SPIE 0856, IECON '87: Industrial Applications of Robotics & Machine Vision, (19 October 1987); https://doi.org/10.1117/12.943036

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