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19 February 2013A CMOS image sensor using floating capacitor load readout operation
In this paper, a CMOS image sensor using floating capacitor load readout operation has been discussed. The floating
capacitor load readout operation is used during pixel signals readout. And this operation has two features: 1. in-pixel
driver transistor drives load capacitor without current sources, 2. parasitic capacitor of pixel output vertical signal line is
used as a sample/hold capacitor. This operation produces three advantages: a smaller chip size, a lower power
consumption, and a lower output noise than conventional CMOS image sensors. The prototype CMOS image sensor has
been produced using 0.18 μm 1-Poly 3-Metal CMOS process technology with pinned photodiodes. The chip size is 2.5
mmH x 2.5 mmV, the pixel size is 4.5 μmH x 4.5 μmV, and the number of pixels is 400H x 300V. This image sensor
consists of only a pixel array, vertical and horizontal shift registers, column source followers of which height is as low as
that of some pixels and output buffers. The size of peripheral circuit is reduced by 90.2 % of a conventional CMOS
image sensor. The power consumption in pixel array is reduced by 96.9 %. Even if the power consumption of column
source follower is included, it reduced by 39.0 %. With an introduction of buried channel transistors as in-pixel driver
transistors, the dark random noise of pixels of the floating capacitor load readout operation CMOS image sensor is 168
μVrms. The noise of conventional image sensor is 466 μVrms; therefore, reduction of 63.8 % of noise was achieved.
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S. Wakashima, Y. Goda, T.L. Li, R. Kuroda, S. Sugawa, "A CMOS image sensor using floating capacitor load readout operation," Proc. SPIE 8659, Sensors, Cameras, and Systems for Industrial and Scientific Applications XIV, 86590I (19 February 2013); https://doi.org/10.1117/12.2004892