Paper
10 April 2013 28nm FD-SOI metal gate profile optimization, CD and undercut monitoring using scatterometry measurement
R. Bouyssou, B. Le Gratiet, P. Gouraud, L. Desvoivres, G. Briend, B. Dumont
Author Affiliations +
Abstract
Gate patterning control for 28nm Fully Depleted Silicon On Insulator (FD-SOI) technology faces several challenges. For lithography and etch , usage of DoseMapper requires extensive and accurate metrology to compute adequate dose recipes. From etch side we will have to control both polysilicon and metal gate CD’s. For device integration it will be extremely important to monitor N and PMOS devices and get appropriate gate profiles since transistor morphology is a key contributor to device performances. In parallel of CD control, thin silicon film on top of buried oxide layer will also require a strict control of its thickness. Scatterometry is the only way to get all these informations from a patterned environment [1]. We will show in this paper how scatterometry has been proven to be accurate enough to support the realization of DOE’s for metal gate profile optimisation at gate patterning without doing hundred’s of TEM. Scatterometry results are correlated to parametric tests and TEM for ultimate validation.
© (2013) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
R. Bouyssou, B. Le Gratiet, P. Gouraud, L. Desvoivres, G. Briend, and B. Dumont "28nm FD-SOI metal gate profile optimization, CD and undercut monitoring using scatterometry measurement", Proc. SPIE 8681, Metrology, Inspection, and Process Control for Microlithography XXVII, 86810R (10 April 2013); https://doi.org/10.1117/12.2010746
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Cited by 2 scholarly publications.
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KEYWORDS
Etching

Critical dimension metrology

Transmission electron microscopy

Metals

Diffractive optical elements

Lithography

Scatterometry

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